Comments on "Filling algorithms and analyses for layout density control"

1209 wire choices are available, because only the look-up table needs to be reconstructed for different choices of wire sizes. The look-up table is constructed very efficiently since every buffer-to-buffer delay is computed incrementally and only once. In other words, as the number of wire sizes increases, the new method is able to gain reduction in delay without need of dramatically increasing computing resources. In Table II, we compare our SPRouting algorithm with the original DP-Routing algorithm. Table II shows the results for the same routing areas in Table I. Buffer insertion and wiresizing are performed simultaneously. Dynamic programming is used to construct the look-up tables. The look-up tables for buffer-to-buffer delays for these test cases are efficiently constructed within 20 s. The technique mentioned in Section III for reducing the size of the BP-graph is implemented in our program. From the table, our method consistently outperforms the original DP-Routing algorithms. With wiresizing, the sizes of the subsolution sets for dynamic programming increase significantly. Furthermore, the same subsolutions are scattered among different nodes in the grid graph, increasing both runtime and space usage. In contrast, our SPRouting algorithm uses a look-up table to avoid storing identical subsolutions and is more efficient than dynamic programming. Dynamic programming based methods are resource intensive if wiresizing is performed simultaneously. Note that in Table II both methods generate the same minimum delay for the buffered path in the test circuits. We have proposed a new shortest path formulation of the Maze Routing with Buffer Insertion and Wiresizing problem. Routing constraints such as wiring obstacles and restrictions on buffer locations are incorporated in this formulation. We showed that finding a buffered minimum delay path is equivalent to finding a shortest path in the BP-graph. We also provided a technique to improve runtime and storage requirement. Experiments show that this formulation provides time and space performance improvements over previously proposed dynamic programming based methods. ACKNOWLEDGMENT The authors would like to thank the Associate Editor and the anonymous reviewers for their helpful comments and suggestions. and buffer insertion with restrictions on buffer locations, " in Proc. [4] W. C. Elmore, " The transient response of damped linear network with particular regard to wideband amplifiers, " J. The Elmore delay as bound for RC trees with generalized input signals, " in Optimal and efficient buffer insertion and wire sizing, " in Proc. [9] , " Optimal wire sizing …